Recommendation ITU-T J.195.3 (03/2024) MAC layer specification for first-generation HiNoC
Summary
History
FOREWORD
Table of Contents
1 Scope
2 References
3 Definitions
     3.1 Terms defined elsewhere
     3.2 Terms defined in this Recommendation
4 Abbreviations and acronyms
5 Conventions
6 MAC layer structure
7 MAC layer frame types
     7.1 Overview
     7.2 Signalling frame
     7.3 Control frame
     7.4 Data frame
     7.5 Encapsulation of HiMAC frames into PHY layer frames
          7.5.1 Encapsulation of signalling frame into PHY layer Pd/Pu frame
          7.5.2 Encapsulation of control frame/data frame into PHY layer Dd/Du frame
     7.6 Bit and octet transmission order in a HiNoC network
8 Convergence sublayer
     8.1 Function of the CS
     8.2 Packing/unpacking
     8.3 Priority mapping
9 Common part sublayer
     9.1 Medium access control and channel allocation
          9.1.1 Overview
          9.1.2 MAP cycle
          9.1.3 Reservation-grant mechanism
     9.2 Node admission
          9.2.1  Overview
          9.2.2 Step 1
          9.2.3 Step 2
          9.2.4 Step 3
          9.2.5 Step 4
          9.2.6 Step 5
          9.2.7 Step 6
          9.2.8 Steady state
     9.3 Link maintenance
          9.3.1 Overview
          9.3.2 Step 1
          9.3.3 Step 2
          9.3.4 Step 3
          9.3.5 Step 4
          9.3.6 Step 5
          9.3.7 Steady state
     9.4 Node quitting/deletion
          9.4.1  Overview
          9.4.2  Active quitting of the NHM/HM
          9.4.3 Passive quitting of the NHM/HM
Annex A  MAC layer constants
Annex B  Format of MAC layer frames
     B.1  Signalling frame format
          B.1.1  Downlink signalling frame format
          B.1.2  Uplink signalling frame format
     B.2  Control/data frame format
Annex C  Ethernet frame packing/unpacking
Appendix I  SDL for MAC layer protocol
     I.1  Overview
     I.2  States of MAC layer entities
     I.3  Symbols and variables
          I.3.1  Symbols
          I.3.2  Variables
     I.4  SDL representation
          I.4.1  HB SDL representation
               I.4.1.1  HB initialization
               I.4.1.2  HB state 0
               I.4.1.3  HB state 1
               I.4.1.4  HB state 2
               I.4.1.5  HB state 3
               I.4.1.6  HB state 4
               I.4.1.7  HB state 5
               I.4.1.8  HB state 6
               I.4.1.9  HB state 7
               I.4.1.10  HB state 8
               I.4.1.11  HB TA1 timeout
               I.4.1.12  HB state 9
               I.4.1.13  HB state 10
               I.4.1.14  HB state 11
               I.4.1.15  HB state 12
               I.4.1.16  HB state 13
               I.4.1.17  HB state 14
               I.4.1.18  HB state 15
               I.4.1.19  HB state 16
               I.4.1.20  HB TM2 timeout
               I.4.1.21  HB quitting/deletion
               I.4.1.22  HB hb_init procedure
               I.4.1.23  HB hb_rst procedure
               I.4.1.24  HB reset_all_timers procedure
          I.4.2 HM SDL representation
               I.4.2.1 HM initialization
               I.4.2.2  HM state 0
               I.4.2.3  HM state 1
               I.4.2.5  HM state 3
               I.4.2.6  HM state 4
               I.4.2.7  HM state 5
               I.4.2.8  HM state 6
               I.4.2.9 HM state 7
               I.4.2.10  HM state 8
               I.4.2.11  HM TA1 timeout
               I.4.2.12  HM state 9
               I.4.2.13  HM state 10
               I.4.2.14  HM state 11
               I.4.2.15  HM state 12
               I.4.2.16  HM state 13
               I.4.2.17  HM state 14
               I.4.2.18  HM state 15
               I.4.2.19  HM state 16
               I.4.2.20  HM TM2 timeout
               I.4.2.21  HM quitting/deletion
               I.4.2.22  HM hm_init procedure
               I.4.2.23  HM hm_rst procedure
               I.4.2.24  HM reset_all_timers procedure
               I.4.2.25 HM backoff_num procedure