Table of Contents - G.8273.3/Y.1368.3 (2020) Amd. 1 (08/2024) -

1	Scope
2	References
3	Definitions
	3.1	Terms defined elsewhere
	3.2	Terms defined in this Recommendation
4	Abbreviations and acronyms
5	Conventions
6	Physical layer frequency performance requirements
	6.1	Synchronous equipment clock interfaces
	6.2	Enhanced synchronous equipment clock interfaces
7	Packet layer performance requirements
	7.1	Constant phase/time error and dynamic time error noise generation
	7.2	Noise tolerance
	7.3	Noise transfer
	7.4	Packet layer transient response and holdover performance
8	Interfaces
	8.1	Phase and time interfaces
	8.2	Frequency interfaces
Annex A � Telecom transparent clock functional model
Appendix I � Traffic load test patterns
Appendix II � Residence time
Appendix III � Performance estimation for cascaded media converters acting as T-TCs
	III.1	Noise generation
	III.2	Noise tolerance
	III.3	Noise transfer
	III.4	Transient response and holdover performance
Appendix IV � Performance estimation of combined T-TSC and T-TC clocks
	IV.1	Noise generation
	IV.2	Noise tolerance
	IV.3	Noise transfer
	IV.4	Transient response and holdover performance