Table of Contents - G.8251 (2022) Amd. 1 (08/2024) -

1	Scope
2	References
3	Definitions
4	Abbreviations and acronyms
5	Conventions
6	Network limits for the maximum output jitter and wander at an OTUk interface
	6.1	Network limits for jitter
	6.2	Network limits for wander
7	Jitter and wander tolerance of network interfaces
	7.1	Jitter and wander tolerance of OTN interfaces
	7.2	Jitter and wander tolerance of client interfaces
Annex A � Specification of the ODUk clock (ODC)
	A.1	Scope
	A.2	Applications
	A.3	Frequency accuracy
	A.4	Pull-in and pull-out ranges
	A.5	Noise generation
	A.6	Noise tolerance
	A.7	Jitter transfer
	A.8	Transient response
	A.9	Delay variation of phase difference accumulation
Appendix I � Relationship between network interface jitter requirements and input jitter tolerance
	I.1	Network interface jitter requirements
	I.2	Input jitter tolerance of network equipment	29
Appendix II � Effect of OTN on the distribution of synchronization via STM-N and synchronous Ethernet clients
	II.1	Introduction
	II.2	Provisional synchronization reference chain
	II.3	Synchronization network limit
	II.4	Variable channel memory
	II.5	Maximum buffer hysteresis
Appendix III � Hypothetical reference model (HRM) for 3R regenerator jitter accumulation
Appendix IV � 3R regenerator jitter accumulation analyses
	IV.1	Introduction
	IV.2	Model 1
	IV.3	Model 2
	Page
	IV.4	Jitter generation of regenerators using parallel serial conversion
Appendix V � Additional background on demapper (ODCp) phase error and demapper wideband jitter generation requirements
	V.1	Introduction
	V.2	Demapper phase error
	V.3	Demapper wideband jitter generation due to gaps produced by fixed overhead in OTUk frame
Appendix VI � OTN atomic functions
	VI.1	Introduction
Appendix VII � Hypothetical reference models (HRMs) for CBRx (SDH and synchronous Ethernet client) and ODUj payload jitter and short-term wander accumulation
	VII.1	Introduction
	VII.2	OTN hypothetical reference models
	VII.3	Impact of the insertion of OTN islands in the ITU-T G.803 synchronization reference chain
Appendix VIII � CBRx and ODUj payload jitter and short-term wander accumulation analyses
	VIII.1	Introduction
	VIII.2	Simulation model
	VIII.3	Jitter and short-term wander simulation results
Appendix IX � Jitter and wander accumulation analysis for transport of Sub1G CBR clients over fgOTN
	IX.1	Introduction
	IX.2	Simulation model
	IX.3	Hypothetical reference models
	IX.4	Simulation cases and inputs
	IX.5	Simulation results
	IX.6	Analysis for STM-4, E1 and VC-n
	IX.7	Details of delay variation of phase difference accumulation
	IX.8	Theoretical analysis about phase detector measurement
Bibliography