Rec. ITU-T G.709.2/Y.1331.2 Corrigendum 1 (09/2020) OTU4 long-reach interface
Summary
History
FOREWORD
Table of Contents
1 Scope
2 References
3 Definitions
     3.1 Terms defined elsewhere
     3.2 Terms defined in this Recommendation
4 Abbreviations and acronyms
5 Conventions
6 Introduction and applications
7 Structure and processes
     7.1 Basic signal structure
     7.2 Processing and information flow
8 OTU4-SC frame
     8.1 Frame structure
     8.2 Bit rate
     8.3 Forward error correction
9 Overhead
10 Scrambling
11 Adaptation of OTU4-SC to a 4-lane interface
Annex A  Forward error correction using 512 × 510 staircase codes
     A.1 Introduction
     A.2 8 × 32640 bit base block (Base Block) and 512 × 510 bit staircase block
     A.3 8 × 32640 bit base block (Base Block) error decorrelator interleaver and de-interleaver
     A.4 Error decorrelator synchronization
     A.5 The 512 × 510 staircase forward error correction code
          A.5.1 Encoding a 512 × 510 staircase forward error correction block
          A.5.2 Decoding a 512 × 510 staircase forward error correction code
          A.5.3 Error correction capability
     A.6 Representation of elements in GF(210)
     A.7 Staircase forward error correction component code mapping
<pre>          A.7.1 Specification of 𝚷𝒅
.
          A.7.2 Parity check Matrix
          A.7.3 Generator matrix
     A.8 Error decorrelator permutation maps
          A.8.1 Generic permutation maps
Annex B  Adaptation of 512 × 510 staircase forward error correction  codes for OTU4-SC FEC
     B.1 OTU4-SC bit and staircase forward error correction specific Base Block mapping relationship
     B.2 Error decorrelator controller synchronization
     B.3 OTU4-SC transmitter and receiver staircase forward error correction processing
Appendix I  Example applications
Appendix II  Generic principles of forward error correction using blockwise-recursively-encoded Staircase FEC
     II.1 Staircase FEC codes: Specifications and basic properties
     II.2 Error decorrelator function
          II.2.1 Error decorrelator datapath
          II.2.2 Error decorrelator implementation
     II.3 Decoding a 512 × 510 staircase forward error correction code
Appendix III  40/38/32 × 64 bit block interleaver
Appendix IV  Generic permutation maps in clause A.8.1 – Numbering according to bit weight
Bibliography
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